1. Field of the Invention
The present invention relates to test devices, and more particularly, to a test device for detecting alignment of deep trench capacitors and active areas in DRAM devices, as well as a test method thereof.
2. Description of the Related Art
FIG. 1 is a layout of conventional deep trench capacitors in a memory device. Deep trench capacitors 10 are disposed under passing word lines. Transistors 14 are electrically coupled to the storage nodes 16 of the capacitors 10 through the diffusion regions 18. The diffusion regions 20 are connected to plugs 22 coupled to bit lines (not shown). The transistors 14 are driven by word lines 12, and the channels thereunder are conductive when appropriate voltages are applied thereto. Consequently, the current produced between the diffusion regions 18 and 20 may flow into or out of the storage nodes 16.
FIG. 2 is a cross-section of FIG. 1. After the deep trench capacitors 10 are completely formed in the substrate, trench isolations are formed in the substrate and deep trench capacitors 10 to define active areas. The word lines 12 are then formed on the substrate, the diffusion regions 18 and 20 are formed in the active areas by word lines 12 during the implant process, and the diffusion regions 18 and 20 are located on both sides of the word lines 12. Finally, plugs 22 are formed on the diffusions 22. The adjacent memory cells may experience current leakage and cell failure, reducing process yield, if active area masks and deep trench capacitors are not aligned accurately.
Therefore, the process yield and reliability of the memory cells can be improved if alignment inaccuracy between the masks of active areas and the deep trench capacitors is controlled within an acceptable range.